1. Field of the Invention
The present invention relates to a controller for supporting a plurality of different memory access.
2. Description of the Background Art
DRAM has evolved from asynchronous DRAM to synchronous DRAM. For example, Fast-Page DRAM and Extended Data Output (EDO) DRAM have evolved to Synchronous Dynamic Random Access Memory (hereinafter abbreviated to SDRAM). Currently, high speed memory banks generally use synchronous source methods for achieving data transmission. By way of an example, Double Data Rate dynamic random access (hereinafter abbreviated to DDR SDRAM) memory bank is one of the methods. In addition, these high speed memory banks require differential signals for data transmission. Therefore, real high access speed for DRAMs requires differential signaling. It is desirous to combine source synchronization with differential signaling.
Furthermore, DRAM market tends to be outpaced in bandwidth by such elements as processor, I/O devices, or graphic add-on devices. This deficiency in bandwidth becomes especially significant for high volume data transfer applications such as Internet applications.
In order to further improve the bandwidth, schemes such as Double Data Rate (DDR), Quad Band Memory (QBM), and Quad Data Rate (QDR) are capable of transmitting four units of data as compared to a single unit for the baseline rate. Further, the above has the advantage of using existing low-cost technology for increasing the bandwidth.
Memory having different data rate or data types generally requires different and separated memory controllers for each and every data type. A number of memory controllers may be required for a single application. Further, more controllers complicate the system and can be space consuming and expensive.
As can be seen, there is a need for a single memory controller which controls different memory types or modes.